Sciweavers

SBACPAD
2008
IEEE
249views Hardware» more  SBACPAD 2008»
14 years 5 months ago
Processing Neocognitron of Face Recognition on High Performance Environment Based on GPU with CUDA Architecture
This work presents an implementation of Neocognitron Neural Network, using a high performance computing architecture based on GPU (Graphics Processing Unit). Neocognitron is an ar...
Gustavo Poli, José Hiroki Saito, Joã...
SBACPAD
2008
IEEE
132views Hardware» more  SBACPAD 2008»
14 years 5 months ago
Aspect-Based Patterns for Grid Programming
The development of grid algorithms is frequently hampered by limited means to describe topologies and lack of support for the invasive composition of legacy components in order to...
Luis Daniel Benavides Navarro, Rémi Douence...
SBACPAD
2008
IEEE
206views Hardware» more  SBACPAD 2008»
14 years 5 months ago
A High Performance Massively Parallel Approach for Real Time Deformable Body Physics Simulation
Single processor technology has been evolving across last decades, but due to physical limitations of chip manufacturing process, the industry is pursuing alternatives to sustain ...
Thiago S. M. C. de Farias, Mozart W. S. Almeida, J...
SBACPAD
2008
IEEE
126views Hardware» more  SBACPAD 2008»
14 years 5 months ago
A Software Transactional Memory System for an Asymmetric Processor Architecture
Due to the advent of multi-core processors and the consequent need for better concurrent programming abstractions, new synchronization paradigms have emerged. A promising one, kno...
Felipe Goldstein, Alexandro Baldassin, Paulo Cento...
SBACPAD
2008
IEEE
127views Hardware» more  SBACPAD 2008»
14 years 5 months ago
Measuring Operating System Overhead on CMT Processors
Numerous studies have shown that Operating System (OS) noise is one of the reasons for significant performance degradation in clustered architectures. Although many studies exami...
Petar Radojkovic, Vladimir Cakarevic, Javier Verd&...
SBACPAD
2008
IEEE
170views Hardware» more  SBACPAD 2008»
14 years 5 months ago
Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-Design
Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to char...
James Poe, Chang-Burm Cho, Tao Li
SBACPAD
2008
IEEE
100views Hardware» more  SBACPAD 2008»
14 years 5 months ago
Selection of the Register File Size and the Resource Allocation Policy on SMT Processors
The performance impact of the Physical Register File (PRF) size on Simultaneous Multithreading processors has not been extensively studied in spite of being a critical shared reso...
Jesús Alastruey, Teresa Monreal, Francisco ...