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29
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ASYNC
2002
IEEE
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ASYNC 2002
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Relative Timing Based Verification of Timed Circuits and Systems
14 years 4 months ago
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jungfrau.usc.edu
Advanced clock-delayed1 and self-resetting domino circuits are becoming increasingly important design styles in aggressive synchronous as well as asynchronous design. Their design...
Peter A. Beerel, Ken S. Stevens, Hoshik Kim
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