Relative Timing Based Verification of Timed Circuits and Systems

Advanced clock-delayed1 and self-resetting domino circuits are becoming increasingly important design styles in aggressive synchronous as well as asynchronous design. Their design is particularly challenging due to the two-sided timing constraints needed to ensure their correctness. This paper proposes a relative-timing based technique to help verify such timed circuits. The main idea is to perform an untimed analysis to identify circuit paths for which delay-ordering constraints ensure that the circuit works. The timing verification of these delays is then reduced to standard simulation or a much simpler bounded delay analysis. The benefit of this approach is three fold. First, it reduced the verification complexity exponentially by avoiding the modeling of explicit clocks. Second, it allows designers to design their circuits very aggressively, ensuring only that the relative path delays are met. Third, it facilitates fast incremental timing verification in response to design changes...

• Type: Conference
• Year: 2002
• Where: ASYNC
• Authors: Peter A. Beerel, Ken S. Stevens, Hoshik Kim
• Keywords: ASYNC 2002, Hardware, Self-resetting Domino Circuits, Timing Verification, Two-sided Timing Constraints