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    ISSS
    1997
    IEEE
    102views Hardware» more  ISSS 1997»
    An Efficient Model for DSP Code Generation: Performance, Code Size, Estimated Energy
    14 years 4 months ago
    An Efficient Model for DSP Code Generation: Performance, Code Size, Estimated Energy
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    This paper presents a model for simultaneous instruction selection, compaction, and register allocation. An arc mapping model along with logical propositions is used to create an ...
    Catherine H. Gebotys
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