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    ISQED
    2008
    IEEE
    120views Hardware» more  ISQED 2008»
    Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation
    14 years 6 months ago
    Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation
    Download  bwrc.eecs.berkeley.edu
    We present an error-tolerant SRAM design optimized for ultra-low standby power. Using SRAM cell optimization techniques, the maximum data retention voltage (DRV) of a 90nm 26kb SR...
    Huifang Qin, Animesh Kumar, Kannan Ramchandran, Ja...
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