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    2005
    IEEE
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    High Level Synthesis of Timed Asynchronous Circuits
    14 years 5 months ago
    High Level Synthesis of Timed Asynchronous Circuits
    Download  www.async.ece.utah.edu
    This paper proposes applying a logic synthesis approach to high level synthesis from SpecC specifications to timed asynchronous gate-level circuits. The state-based logic synthes...
    Tomohiro Yoneda, Atsushi Matsumoto, Manabu Kato, C...
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