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36
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ICCAD
2005
IEEE
176
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ICCAD 2005
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Statistical gate sizing for timing yield optimization
14 years 8 months ago
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homepages.cae.wisc.edu
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...
Debjit Sinha, Narendra V. Shenoy, Hai Zhou
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