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    VLSI
    2005
    Springer
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    Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits
    14 years 5 months ago
    Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits
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    Quasi delay insensitive circuits are functionally independent of delays in gates and wires (except for some particular wires). Such asynchronous circuits offer high robustness but...
    Bertrand Folco, Vivian Brégier, Laurent Fes...
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