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32
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ITC
1997
IEEE
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ITC 1997
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Testability Analysis and ATPG on Behavioral RT-Level VHDL
14 years 4 months ago
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www.cad.polito.it
This paper proposes an environment to address Testability Analysis and Test Pattern Generation on VHDL descriptions at the RT-level. The proposed approach, based on a suitable fau...
Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
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