Testability Analysis and ATPG on Behavioral RT-Level VHDL

This paper proposes an environment to address Testability Analysis and Test Pattern Generation on VHDL descriptions at the RT-level. The proposed approach, based on a suitable fault model and an ATPG algorithm, is experimentally shown to provide a good estimate of the final gate-level fault coverage, and to give test patterns with excellent fault coverage properties. The approach, being based on an abstract representation, is particularly suited for large circuits, where gatelevel ATPGs are often inefficient.

• Type: Conference
• Year: 1997
• Where: ITC
• Authors: Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
• Keywords: Fault Coverage, Hardware, ITC 1997, Suitable Fault Model, Test Patterns