Sciweavers

    ISLPED
    1999
    ACM
    143views Hardware» more  ISLPED 1999»
    Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation
    14 years 11 months ago
    Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation
    Download  iacoma.cs.uiuc.edu
    Modern microprocessors employ one or two levels of on-chip cachesto bridge the burgeoning speeddisparities between the processor and the RAM. These SRAM caches are a major source ...
    Kanad Ghose, Milind B. Kamble
    claim paper
    Read More »
    Explore & Download
    Proceedings Preprints Top 5 Ranked Papers Publications Books Software Tutorials Presentations Lectures Notes Datasets
    Productivity Tools
    International On-screen Keyboard Graphical Social Symbols OCR Text Recognition CSS3 Style Generator Web Page to PDF Web Page to Image PDF Split PDF Merge Latex Equation Editor Sci2ools
    Document Tools
    PDF to Text PDF to Postscript PDF to Thumbnails Excel to PDF Word to PDF Postscript to PDF PowerPoint to PDF Latex to Word Repair Corrupted PDF
    Image Tools
    JPG to PS JPG to PDF Extract Images from PDF Image Converter
    Sciweavers
    About Community Cookies Privacy Policy Terms of Use

    Copyright © Sciweavers LLC, 2009-2025, USA.