This paper presents a partitioning and allocation algorithm for an iterative stream compiler, targeting heterogeneous multiprocessors with constrained distributed memory and any c...
In this paper we address the issue of making a program reversible in terms of spatial complexity. Spatial complexity is the amount of memory/register locations required for perfor...
The issues of compiler optimization phase ordering and selection present important challenges to compiler developers in several domains, and in particular to the speed, code size,...
Prasad A. Kulkarni, Michael R. Jantz, David B. Wha...
The automotive industry has a growing demand for the seamless integration of safety analysis tools into the model-based development toolchain for embedded systems. This requires t...
Chip multiprocessors (CMPs) are expected to be the building blocks for future computer systems. While architecting these emerging CMPs is a challenging problem on its own, program...
Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin,...
Concurrent Action-Oriented Specifications (CAOS) model the behavior of a synchronous hardware circuit as asynchronous guarded at an abstraction level higher than the Register Tran...
In this paper, we propose a hybrid-level flash translation layer (FTL) called RNFTL (Reuse-Aware NFTL) to improve the endurance and space utilization of NAND flash memory. Our bas...
Yi Wang, Duo Liu, Meng Wang, Zhiwei Qin, Zili Shao...
We propose a new design for an energy-efficient hardware transactional memory (HTM) system for power-aware embedded devices. Prior hardware transactional memory designs proposed a ...
Cesare Ferri, Samantha Wood, Tali Moreshet, R. Iri...
Abstract. Stream programming is a promising way to expose concurrency to the compiler. A stream program is built from kernels that communicate only via point-to-point streams. The ...
We present a fine-grain dynamic instruction placement algorithm for small L0 scratch-pad memories (spms), whose unit of transfer can be an individual instruction. Our algorithm ca...