Sciweavers

DATE
2006
IEEE
86views Hardware» more  DATE 2006»
14 years 5 months ago
Synthesis of system verilog assertions
In recent years, Assertion-Based Verification is being widely accepted as a key technology in the pre-silicon validation of system-on-chip(SOC) designs. The System Verilog langua...
Sayantan Das, Rizi Mohanty, Pallab Dasgupta, P. P....