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    RTCSA
    1999
    IEEE
    103views Embedded Systems» more  RTCSA 1999»
    Pipeline Timing Analysis Using a Trace-Driven Simulator
    14 years 3 months ago
    Pipeline Timing Analysis Using a Trace-Driven Simulator
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    In this paper we present a technique for Worst-Case Execution Time WCET analysis for pipelined processors. Our technique uses a standard simulator instead of special-purpose pipel...
    Jakob Engblom, Andreas Ermedahl
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