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GLVLSI
2008
IEEE
157views VLSI» more  GLVLSI 2008»
14 years 7 months ago
Coverage-driven automatic test generation for uml activity diagrams
Due to the increasing complexity of today’s embedded systems, the analysis and validation of such systems is becoming a major challenge. UML is gradually adopted in the embedded...
Mingsong Chen, Prabhat Mishra, Dhrubajyoti Kalita
AICCSA
2008
IEEE
290views Hardware» more  AICCSA 2008»
14 years 7 months ago
Test of preemptive real-time systems
Time Petri nets with stopwatches not only model system/environment interactions and time constraints. They further enable modeling of suspend/resume operations in real-time system...
Noureddine Adjir, Pierre de Saqui-Sannes, Kamel Mu...
ICST
2009
IEEE
14 years 7 months ago
WS-TAXI: A WSDL-based Testing Tool for Web Services
Web Services (WSs) are the W3C-endorsed realization of the Service-Oriented Architecture (SOA). Since they are supposed to be implementation-neutral, WSs are typically tested blac...
Cesare Bartolini, Antonia Bertolino, Eda Marchetti...
ICSE
2009
IEEE-ACM
14 years 7 months ago
WISE: Automated test generation for worst-case complexity
Program analysis and automated test generation have primarily been used to find correctness bugs. We present complexity testing, a novel automated test generation technique to ...
Jacob Burnim, Sudeep Juvekar, Koushik Sen
FASE
2009
Springer
14 years 7 months ago
Reducing the Costs of Bounded-Exhaustive Testing
Abstract. Bounded-exhaustive testing is an automated testing methodology that checks the code under test for all inputs within given bounds: first the user describes a set of test...
Vilas Jagannath, Yun Young Lee, Brett Daniel, Dark...
ATS
2009
IEEE
132views Hardware» more  ATS 2009»
14 years 7 months ago
On Improving Diagnostic Test Generation for Scan Chain Failures
In this paper, we present test generation procedures to improve scan chain failure diagnosis. The proposed test generation procedures improve diagnostic resolution by using multi-...
Xun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. ...
ATS
2009
IEEE
99views Hardware» more  ATS 2009»
14 years 7 months ago
Test Generation for Designs with On-Chip Clock Generators
High performance designs often use the on-chip device PLLs for accurate test clock generation during testing. The on-chip clock generator is designed in a programmable way to faci...
Xijiang Lin, Mark Kassab