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ICCAD
1994
IEEE
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ICCAD 1994
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A timing analysis algorithm for circuits with level-sensitive latches
14 years 4 months ago
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www.cs.york.ac.uk
For a logic design with level-sensitive latches, we need to validate timing signal paths which may flush through several latches. We developed efficient algorithms based on the mo...
Jin-fuw Lee, Donald T. Tang, C. K. Wong
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