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    DATE
    2005
    IEEE
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    On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs
    14 years 10 months ago
    On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs
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    Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected b...
    Fernanda Lima Kastensmidt, Luca Sterpone, Luigi Ca...
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