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    TODAES
    2002
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    Estimation of state line statistics in sequential circuits
    14 years 8 days ago
    Estimation of state line statistics in sequential circuits
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    Vikram Saxena, Farid N. Najm, Ibrahim N. Hajj
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    TODAES
    2002
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    BDD-based logic synthesis for LUT-based FPGAs
    14 years 8 days ago
    BDD-based logic synthesis for LUT-based FPGAs
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    Navin Vemuri, Priyank Kalla, Russell Tessier
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    TODAES
    2002
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    Partitioning sequential programs for CAD using a three-step approach
    14 years 8 days ago
    Partitioning sequential programs for CAD using a three-step approach
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    Frank Vahid
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    TODAES
    2002
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    Fast placement approaches for FPGAs
    14 years 8 days ago
    Fast placement approaches for FPGAs
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    Russell Tessier
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    TODAES
    2002
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    Prefetching for improved bus wrapper performance in cores
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    Prefetching for improved bus wrapper performance in cores
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    Roman L. Lysecky, Frank Vahid
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    TODAES
    2002
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    Cluster assignment for high-performance embedded VLIW processors
    14 years 8 days ago
    Cluster assignment for high-performance embedded VLIW processors
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    Viktor S. Lapinskii, Margarida F. Jacome, Gustavo ...
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    TODAES
    2002
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    Cluster-aware iterative improvement techniques for partitioning large VLSI circuits
    14 years 8 days ago
    Cluster-aware iterative improvement techniques for partitioning large VLSI circuits
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    Shantanu Dutt, Wenyong Deng
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    TODAES
    2002
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    A fast algorithm for context-aware buffer insertion
    14 years 8 days ago
    A fast algorithm for context-aware buffer insertion
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    Ashok Jagannathan, Sung-Woo Hur, John Lillis
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    TODAES
    2002
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    Constructing and exploiting linear schedules with prescribed parallelism
    14 years 8 days ago
    Constructing and exploiting linear schedules with prescribed parallelism
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    Alain Darte, Robert Schreiber, B. Ramakrishna Rau,...
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    TODAES
    2002
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    False-noise analysis using logic implications
    14 years 8 days ago
    False-noise analysis using logic implications
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    ct Cross-coupled noise analysis has become a critical concern in today's VLSI designs. Typically, noise analysis makes an assumption that all aggressing nets can simultaneousl...
    Alexey Glebov, Sergey Gavrilov, David Blaauw, Vlad...
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