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31
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ASPDAC
1995
ACM
108
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ASPDAC 1995
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Transistor reordering rules for power reduction in CMOS gates
14 years 4 months ago
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www.cecs.uci.edu
— The goal of transistor reordering for a logic gate is to reduce the propagation delay as well as the charging and discharging of internal capacitances to achieve low power cons...
Wen-Zen Shen, Jiing-Yuan Lin, Fong-Wen Wang
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