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    3DIC
    2009
    IEEE
    279views Hardware» more  3DIC 2009»
    Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits
    14 years 7 months ago
    Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits
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    Abstract—Modeling parasitic parameters of Through-SiliconVia (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circ...
    Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, ...
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