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    ICCAD
    2005
    IEEE
    133views Hardware» more  ICCAD 2005»
    Gate sizing using incremental parameterized statistical timing analysis
    14 years 8 months ago
    Gate sizing using incremental parameterized statistical timing analysis
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    — As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as sta...
    Matthew R. Guthaus, Natesan Venkateswaran, Chandu ...
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