ICCD
2007
IEEE
14 years 5 months ago
2007
IEEE
A methodology for constructing circuit-level mismatch models and performing yield optimization is presented for CMOS analog circuits. The methodology combines statistical techniqu...
DAC
2007
ACM
15 years 16 days ago
2007
ACM
In this paper, we propose TROY, the first track router with yield-driven wire planning to optimize yield loss due to random defects. As the probability of failure (POF) computed f...