Fault Tolerant CMOS Logic Using Ternary Gates

In this paper we present fault tolerant CMOS logic using redundancy and ternary signals. The ternary gates are implemented using recharge logic which can be exploited in binary and multiple-valued logic (MVL). Signals are processed through capacitors in such a way that the logic operation of a gate is independent of the DC voltage applied on the inputs. By combining signals through capacitors stuck on/stuck off and stuck at faults are not destructive when redundancy is applied. Simulated data for 130nm and 0.35µm CMOS processes are given.

• Type: Conference
• Year: 2007
• Where: ISMVL
• Authors: Yngvar Berg, Renè Jensen, Johannes Goplen Lomsdalen, Henning Gundersen, Snorre Aunet
• Keywords: Artificial Intelligence, Fault Tolerant Cmos, ISMVL 2007, Logic, Ternary Signals