CAPSULE: Hardware-Assisted Parallel Execution of Component-Based Programs

Since processor performance scalability will now mostly be achieved through thread-level parallelism, there is a strong incentive to parallelize a broad range of applications, including those with complex control flow and data structures. And writing parallel programs is a notoriously difficult task. Beyond processor performance, the architect can help by facilitating the task of the programmer, especially by simplifying the model exposed to the programmer. In this article, among the many issues associated with writing parallel programs, we focus on finding the appropriate parallelism granularity, and efficiently mapping tasks with complex control and data flow to threads. We propose to relieve the user and compiler of both tasks by delegating the parallelization decision to the architecture at run-time, through a combination of hardware and software support and a tight dialogue between both. For the software support, we leverage an increasingly popular approach in software engineerin...

• Type: Journal
• Year: 2006
• Where: MICRO
• Authors: Pierre Palatin, Yves Lhuillier, Olivier Temam
• Keywords: Complex Control, Hardware, MICRO 2006, Parallel Programs, Processor Performance