A Study of the Performance Potential for Dynamic Instruction Hints Selection

Abstract. Instruction hints have become an important way to communicate compile-time information to the hardware. They can be generated by the compiler and the post-link optimizer to reduce cache misses, improve branch prediction and minimize other performance bottlenecks. This paper discusses different instruction hints available on modern processor architectures and shows the potential performance impact on many benchmark programs. Some hints can be effectively selected at compile time with profile feedback. However, since the same program executable can behave differently on various inputs and performance bottlenecks may change on different micro-architectures, significant performance opportunities can be exploited by selecting instruction hints dynamically.

• Type: Conference
• Year: 2006
• Where: APCSAC
• Authors: Rao Fu, Jiwei Lu, Antonia Zhai, Wei-Chung Hsu
• Keywords: APCSAC 2006, Different Instruction Hints, Instruction Hints, Performance Bottlenecks