GALS networks on chip: a new solution for asynchronous delay-insensitive links

In this paper a cost effective solution for asynchronous delay-insensitive on-chip communication is proposed. Our solution is based on the Berger coding scheme and allows to obtain a very low wire overhead. For instance, the results of our evaluation show that a 64-bit link can be built paying a wire overhead of 10% and 30 equivalent two-input gates per wire. As a general rule, when the number of bits to be transmitted increases, the wire overhead decreases and the gate overhead remains almost the same.

• Type: Conference
• Year: 2006
• Where: DATE
• Authors: G. Campobello, M. Castano, C. Ciofi, Daniele Mangano
• Keywords: DATE 2006, Hardware, Low Wire Overhead, Wire Overhead, Wire Overhead Decreases