A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs

This paper describes a fast-lock mixed-mode delaylocked loop (MMDLL) for wide-range operation and multiphase outputs. The architecture of the proposed DLL uses the mixed-mode time-to-digital converter (TDC) scheme for frequency range selector, a start-up circuit and coarse tune circuit to offer the faster lock time. And the multi-controlled delay cell for voltage-controlled delay line (VCDL) was used to provide the wide locked range and low-jitter performance. The charge pump circuit is implemented by digital controlled scheme to reach bandwidth tracking. The chip has been fabricated using the TSMC 0.25-µm single-poly five-metal CMOS process with a 2.5 V power supply voltage. From the measurement results, this DLL can operate correctly when the input clock frequency is changed from 32 to 320 MHz and generate ten-phase clocks within just one clock cycle. Moreover, the proposed DLL can solve the problem of the false locking associated with conventional DLL’s and wide-range operation....

• Type: Conference
• Year: 2006
• Where: DATE
• Authors: Kuo-Hsing Cheng, Yu-lung Lo
• Keywords: Clock Cycles, DATE 2006, Hardware, Wide-range Dll, Wide-range Operation