ASIP-based multiprocessor SoC design for simple and double binary turbo decoding

This paper presents a new multiprocessor platform for high throughput turbo decoding. The proposed platform is based on a new configurable ASIP combined with an efficient memory and communication interconnect scheme. This Application-Specific Instruction-set Processor has an SIMD architecture with a specialized and extensible instruction-set and 5-stages pipeline control. The attached memories and communication interfaces enable the design of efficient multiprocessor architectures. These multiprocessor architectures benefit from the recent shuffling technique introduced in the turbo-decoding field to reduce communication latency. The major characteristics of the proposed platform are its flexibility and scalability which make it reusable for various standards and operating modes. Results obtained for double binary DVB-RCS turbo codes demonstrate a 100 Mbit/s throughput using 16-ASIP multiprocessor architecture.

• Type: Conference
• Year: 2006
• Where: DATE
• Authors: Olivier Muller, Amer Baghdadi, Michel Jézéquel
• Keywords: 16-ASIP Multiprocessor Architecture, DATE 2006, Efficient Multiprocessor Architectures, Hardware, Multiprocessor Architecture