Restructuring field layouts for embedded memory systems

In many computer systems with large data computations, the delay of memory access is one of the major performance bottlenecks. In this paper, we propose an enhanced field remapping scheme for dynamically allocated structures in order to provide better locality than conventional field layouts. Our proposed scheme reduces cache miss rates drastically by aggregating and grouping fields from multiple instances of the same structure, which implies the performance improvement and power reduction. Our methodology will become more important in the design space exploration, especially as the embedded systems for data oriented application become prevalent. Experimental results show that average L1 and L2 data cache misses are reduced by 23% and 17%, respectively. Due to the enhanced localities, our remapping achieves 13% faster execution time on average than original programs. It also reduces power consumption by 18% for data cache.

• Type: Conference
• Year: 2006
• Where: DATE
• Authors: Keoncheol Shin, Jungeun Kim, Seonggun Kim, Hwansoo Han
• Keywords: Data Cache, DATE 2006, Enhanced field Remapping, Hardware, Scheme Reduces Cache