Hardware/Software Co-design Applied to Reed-Solomon Decoding for the DMB Standard

This paper addresses the implementation of ReedSolomon decoding for battery-powered wireless devices. The scope of this paper is constrained by the Digital Media Broadcasting (DMB). The most critical element of the Reed-Solomon algorithm is implemented on two different reconfigurable hardware architectures: an FPGA and a coarse-grained architecture: the Montium, The remaining parts are executed on an ARM processor. The results of this research show that a co-design of the ARM together with an FPGA or a Montium leads to a substantial decrease in energy consumption. The energy consumption of syndrome calculation of the ReedSolomon decoding algorithm is estimated for an FPGA and a Montium by means of simulations. The Montium proves to be more efficient.

• Type: Conference
• Year: 2006
• Where: DSD
• Authors: Arjan C. Dam, Michel G. J. Lammertink, Kenneth C. Rovers, Johan Slagman, Arno M. Wellink
• Keywords: Battery-powered Wireless Devices, DSD 2006, Energy Consumption, FPGA, Hardware