An Asynchronous PLA with Improved Security Characteristics

Programmable logic arrays (PLAs) present an alternative to logic-gate based design. We propose the transistor level structure of a PLA for single-rail asynchronous applications. The geometrically regular layout together with the deployment of dynamic logic help us fine-tune the PLA to enhance its resistance to side-channel attacks, while parity prediction and checking is employed to protect against malicious fault injection. Finally, we demonstrate how our PLAs can be used as building blocks of large-scale systems with good security characteristics, when combined with special return-to-zero asynchronous latches.

• Type: Conference
• Year: 2006
• Where: DSD
• Authors: Petros Oikonomakos, Simon W. Moore
• Keywords: DSD 2006, Hardware, Programmable Logic Arrays, Return-to-zero Asynchronous Latches, Single-rail Asynchronous Applications