Branch predictor guided instruction decoding

Fast instruction decoding is a challenge for the design of CISC microprocessors. A well-known solution to overcome this problem is using a trace cache. It stores and fetches already decoded instructions, avoiding the need for decoding them again. However, implementing a trace cache involves an important increase in the fetch architecture complexity. In this paper, we propose a novel decoding architecture that reduces the fetch engine implementation cost. Instead of using a special-purpose buffer like the trace cache, our proposal stores frequently decoded instructions in the memory hierarchy. The address where the decoded instructions are stored is kept in the branch prediction mechanism, enabling it to guide our decoding architecture. This makes it possible for the processor front-end to fetch already decoded instructions from memory instead of the original nondecoded instructions. Our results show that an 8-wide superscalar processor achieves an average 14% performance improvement ...

• Type: Conference
• Year: 2006
• Where: IEEEPACT
• Authors: Oliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero
• Keywords: Fetch Architecture, Fetch Architecture Complexity, Hardware, IEEEPACT 2006, Trace Cache