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    VHDL to FPGA automatic IP-Core generation: a case study on Xilinx design flow

    14 years 5 months ago
    VHDL to FPGA automatic IP-Core generation: a case study on Xilinx design flow
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    Fabrizio Ferrandi, G. Ferrara, R. Palazzo, Vincenz
    claim paper
    Added 11 Jun 2010
    Updated 11 Jun 2010
    Type Conference
    Year 2006
    Where IPPS
    Authors Fabrizio Ferrandi, G. Ferrara, R. Palazzo, Vincenzo Rana, Marco D. Santambrogio
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