Designing secure systems on reconfigurable hardware

The extremely high cost of custom ASIC fabrication makes FPGAs an attractive alternative for deployment of custom hardware. Embedded systems based on reconfigurable hardware integrate many functions onto a single device. Since embedded designers often have no choice but to use soft IP cores obtained from third parties, the cores operate at different trust levels, resulting in mixed trust designs. The goal of this project is to evaluate recently proposed security primitives for reconfigurable hardware by building a real embedded system with several cores on a single FPGA and implementing these primitives on the system. Overcoming the practical problems of integrating multiple cores together with security mechanisms will help us to develop realistic security policy specifications that drive enforcement mechanisms on embedded systems. Categories and Subject Descriptors: B.3.2 [MEMORY STRUCTURES]: Design Styles--Virtual Memory; B.7.1 [INTEGRATED CIRCUITS]: Types and Design Styles--Gate Ar...

• Type: Journal
• Year: 2008
• Where: TODAES
• Authors: Ted Huffmire, Brett Brotherton, Nick Callegari, Jonathan Valamehr, Jeff White, Ryan Kastner, Timothy Sherwood
• Keywords: Cores, Embedded Systems, Reconfigurable Hardware, TODAES 2008