A high-speed low-energy dynamic PLA using an input-isolation scheme

— Recently, there has been renewed interest in structured logic arrays due to a number of inherent advantages. However, before they will be more widely adopted, structured logic arrays must be able to compete with standard ASIC designs. This paper proposes a CMOS PLA based on a dynamic NOR architecture that uses an input-isolation technique along with a latch-based sense amplifier to achieve both high operating speed and low-energy consumption. The proposed architecture is designed and simulated in a 0.18µm CMOS technology. It improves the delay by 10% compared with the fastest reported PLA. It also achieves the lowest power-delay product of all other reported dynamic PLAs.

• Type: Conference
• Year: 2006
• Where: ISCAS
• Authors: Reza Molavi, Shahriar Mirabbasi, Resve A. Saleh
• Keywords: CMOS PLA, Fastest Reported Pla, ISCAS 2006, Structured Logic Arrays