A novel ternary more, less and equality circuit using recharged semi-floating gate devices

— This paper presents a novel Ternary More, Less and Equality (MLE) Circuit implemented with Recharged SemiFloating Gate Transistors. The circuit is a ternary application, and ternary structures may offer the fastest search in a tree structure. The circuit has two ternary inputs, and one ternary output which will be a comparison of the two ternary inputs. The circuit is a useful building block for use in a search tree application. The circuit is simulated by using Cadence R Analog Design Environment with CMOS090 GP process parameters from STMicroelectronics, a 90 nm General Purpose Bulk CMOS Process with 7 metal layers. The circuit operates at a 1 GHz clock frequency. The supply voltage is +/- 0.5 Volt. All capacitors are metal plate capacitors, based on a vertical coupling capacitance between stacked metal plates.

• Type: Conference
• Year: 2006
• Where: ISCAS
• Authors: Henning Gundersen, Yngvar Berg
• Keywords: ISCAS 2006, Ternary Application, Ternary Inputs, Ternary Structures