Vertex cache of programmable geometry processor for mobile multimedia application

Vertex cache of programmable geometry processor The proposed architecture of vertex cache is divided into is proposed and implemented. The proposed vertex cache is pre-TnL vertex cache and post-TnL vertex cache; TnL organized into pre-TnL vertex cache and post-TnL vertex implies Transformation and Lighting, i.e. geometric cache. The pre-TnL vertex cache reduces 32.8% geometry operations. Before geometry processing, the pre-TnL vertex bandwidth by reusing fetched vertices with 32 entries. The cache stores 32 vertices and fetches 4 consecutive vertices post-TnL vertex cache improves the performance of a from an external memory on a miss. It reduces on the geometry processor by reusing recently processed vertices with average of 32.8% geometry bandwidth by reusing and

• Type: Conference
• Year: 2006
• Where: ISCAS
• Authors: Kyusik Chung, Chang-Hyo Yu, Lee-Sup Kim
• Keywords: ISCAS 2006, Post-TnL Vertex Cache, Pre-TnL Vertex Cache, Vertex Cache