A portable all-digital pulsewidth control loop for SOC applications

—A cell-based all-digital PWCL is presented in this paper. To improve design effort as well as facilitate systemlevel integration, the new design can be developed in hardware description language (HDL) and implemented with standard-cell libraries, therefore, easily portable between technologies. In addition, a high-resolution architecture is designed to enhance pulsewidth precision. For different requirements of applications, the characteristic of scalable modulating range allows hardware decision in early stage. The proposed methodology has been proven at UMC 0.18um CMOS technology. When operated at 350 MHz, the pulse width acquisition ranges from 10% to 85% with 0.9% steps.

• Type: Conference
• Year: 2006
• Where: ISCAS
• Authors: Wei Wang, I-Chyn Wey, Chia-Tsun Wu, An-Yeu Wu
• Keywords: Cell-based All-digital Pwcl, Facilitate Systemlevel Integration, ISCAS 2006, Scalable Modulating Range