DF-DICE: a scalable solution for soft error tolerant circuit design

—The Delay Filtered Dual Interlocked storage Cell (DF-DICE) offers a scalable solution in different radiation environments for soft error mitigation. The area and speed performance for five different single event transient thresholds have been evaluated. The results show that the cost of soft error mitigation is minimal for terrestrial environments (overall area penalty less than 14% and speed penalty within 6% for flip-flop based typical designs) while it is larger for space environments (overall area penalty up to 30% and speed penalty up to 13% for flip-flop based typical designs). The logic of a conventional Application Specific Integrated Circuit (ASIC) can easily be converted to a soft-error tolerant design by replacing the existing storage elements with the respective DF- DICE elements.

• Type: Conference
• Year: 2006
• Where: ISCAS
• Authors: Riaz Naseer, Jeff Draper
• Keywords: Dual Interlocked Storage, ISCAS 2006, Overall Area Penalty, Soft Error Mitigation