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ISCAS
2006
IEEE

Phase-tracking loop based on delta-sigma oversampling architecture

14 years 5 months ago
Phase-tracking loop based on delta-sigma oversampling architecture
Abstract— This paper presents a new oversampling architecture for implementing phase-tracking loop that is commonly utilized for position sensors such that synchro, resolver, and incremental encoder. This architecture consists of the cascade connection of three stage: coarse-quantizing and oversampling modulation, direct signal processing, and decimation filtering. It is expected that the oversampling strategy and the signal processing increase the resolution of detecting phase as well as oversampling A/D converters. This paper shows an simplest design of the signal processing circuit and some simulation results.
Yuichiro Orino, Minoru Kuribayashi Kurosawa, Takas
Added 12 Jun 2010
Updated 12 Jun 2010
Type Conference
Year 2006
Where ISCAS
Authors Yuichiro Orino, Minoru Kuribayashi Kurosawa, Takashi Katagiri
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