Compiler-Directed Power Density Reduction in NoC-Based Multi-Core Designs

As transistor counts keep increasing and clock frequencies rise, high power consumption is becoming one of the most important obstacles, preventing further scaling and performance improvements. While high power consumption brings many problems with it, high power density and thermal hotspots are maybe two of the most important ones. Current architectures provide several circuit based solutions to cope with thermal emergencies when they occur but exercising them frequently can lead to significant performance losses. This paper proposes a compiler-based approach that balances the computational workload across the processors of an NoC based chip multiprocessor such that the chances of experiencing a thermal emergency at runtime are reduced. Our results show that the proposed approach cuts the number of runtime thermal emergencies by 42% on the average on benchmarks tested. c 2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for...

• Type: Conference
• Year: 2006
• Where: ISQED
• Authors: Sri Hari Krishna Narayanan, Mahmut T. Kandemir, Ozcan Ozturk
• Keywords: Hardware, ISQED 2006, Runtime Thermal Emergencies, Thermal Emergencies, Thermal Hotspots