Diagonal routing in high performance microprocessor design

This paper presents a diagonal routing method which is applied to an actual microprocessor prototype chip. While including the layout functions for the conventional Manhattan routing with horizontal and vertical directions, a new diagonal routing capability is added as one of the routing functions. With this enhancement, diagonal routing becomes an additional strategy for improving delays of critical paths in the microprocessor design. This method was applied to the prototype chip of the Fujitsu SPARC64 microprocessor with two CPU cores using 90nm process technology. By applying the diagonal routing to long distance nets, net length is reduced by 36% per net on average. When the diagonal routing is applied to a critical path, path delay is improved by as much as about 14 pico-seconds per net on a path. This improvement is more than the delay of a gate with no load. This prototype chip proved that our method was effective in reducing the total net length and improving path delays.

• Type: Conference
• Year: 2006
• Where: ASPDAC
• Authors: Noriyuki Ito, Hideaki Katagiri, Ryoichi Yamashita, Hiroshi Ikeda, Hiroyuki Sugiyama, Hiroaki Komatsu, Yoshiyasu Tanamura, Akihiro Yoshitake, Kazuhiro Nonomura, Kinya Ishizaka, Hiroaki Adachi, Yutaka Mori, Yutaka Isoda, Yaroku Sugiyama
• Keywords: ASPDAC 2006, Diagonal Routing, Diagonal Routing Method, Prototype Chip