Worst case execution time analysis for synthesized hardware

- We propose a hardware performance estimation flow for fast design space exploration, based on worst-case execution time analysis algorithms for software analysis. Test cases on some real-world applications show that our flow provides a tight upper bound of the execution time, and many useful hints to the designer.

• Type: Conference
• Year: 2006
• Where: ASPDAC
• Authors: Jun-hee Yoo, Xingguang Feng, Kiyoung Choi, Eui-Young Chung, Kyu-Myung Choi
• Keywords: ASPDAC 2006, Execution Time, Performance Estimation Flow, Worst-case Execution Time