Power constrained design optimization of analog circuits based on physical gm/ID characteristics

This paper presents a transistor optimization methodology for low-power analog integrated CMOS circuits, relying on the physics-based gm/ID characteristics as a design optimization guide. Our custom layout tool LIT implements and uses the ACM MOS compact model in the optimization loop.The methodology is implemented for automation within LIT and exploits all design space through the simulated annealing optimization process, providing solutions close to optimum with a single technology-dependent curve and accurate expressions for transconductance and current valid in all operation regions.The compact model itself contributes to convergence and to optimized implementations, since it has analytic expressions which are continuous in all current regimes, including weak and moderate inversion.The advantage of constraining the optimization within a power budget is of great importance for low-power CMOS. As examples we show the optimization results obtained with LIT, resulting in significant p...

• Type: Conference
• Year: 2006
• Where: SBCCI
• Authors: Alessandro Girardi, Sergio Bampi
• Keywords: Optimization Loop.The Methodology, SBCCI 2006, Simulated Annealing Optimization, Transistor Optimization Methodology