Multithreaded Extension to Multicluster VLIW Processors for Embedded Applications

Instruction Level Parallelism (ILP) extraction for multicluster VLIW processors is a very hard task. In this paper, we propose a retargetable architecture that can exploit ILP and thread level parallelism jointly, thus allowing an easier parallelism extraction and improving the performance with respect to traditional multicluster VLIW processors.

• Type: Conference
• Year: 2005
• Where: DATE
• Authors: Domenico Barretta, William Fornaciari, Mariagiovanna Sami, Daniele Bagni
• Keywords: DATE 2005, Hardware, Instruction Level Parallelism, Level Parallelism, Multicluster Vliw Processors