Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters

This paper suggests a practical “hybrid” synthesis methodology which integrates designer-derived analytical models for system-level description with simulation-based models at the circuit level. We show how to optimize stageresolution to minimize the power in a pipelined ADC. Exploration (via detailed synthesis) of several ADC configurations is used to show that a 4-3-2… resolution distribution uses the least power for a 13-bit 40 MSPS converter in a 0.25 µm CMOS process.

• Type: Conference
• Year: 2005
• Where: DATE
• Authors: Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar, Tamal Mukherjee
• Keywords: DATE 2005, Designer-derived Analytical Models, Hardware, Pipelined Adc, µm Cmos Process