Hardware Acceleration of Hidden Markov Model Decoding for Person Detection

This paper explores methods for hardware acceleration of Hidden Markov Model (HMM) decoding for the detection of persons in still images. Our architecture exploits the inherent structure of the HMM trellis to optimise a Viterbi decoder for extracting the state sequence from observation features. Further performance enhancement is obtained by computing the HMM trellis states in parallel. The resulting hardware decoder architecture is mapped onto a field programmable gate array (FPGA). The performance and resource usage of our design is investigated for different levels of parallelism. Performance advantages over software are evaluated. We show how this work contributes to a real-time system for person-tracking in video-sequences.

• Type: Conference
• Year: 2005
• Where: DATE
• Authors: Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk
• Keywords: DATE 2005, Hardware, Hardware Decoder Architecture, HMM Trellis, HMM Trellis States