Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL

This paper describes two research projects that develop new low-cost techniques for testing devices with multiple high-speed (2 to 5 Gbps) signals. Each project uses commercially available components to keep costs low, yet achieves performance characteristics comparable to (and in some ways exceeding) more expensive ATE. A common CMOS FPGA-based logic core provides flexibility, adaptability, and communication with controlling computers while customized positive emittercoupled logic (PECL) achieves multi-gigahertz data rates with about +25ps timing accuracy.

• Type: Conference
• Year: 2005
• Where: DATE
• Authors: David C. Keezer, C. Gray, A. M. Majid, N. Taher
• Keywords: +25ps Timing Accuracy, CMOS FPGA-based Logic, DATE 2005, Hardware, Positive Emittercoupled Logic