A Coprocessor for Accelerating Visual Information Processing

Visual information processing will play an increasingly important role in future electronics systems. In many applications, e.g. video surveillance cameras, data throughput of microprocessors is not sufficient and power consumption is too high. Instruction profiling on a typical test algorithm has shown that pixel address calculations are the dominant operations to be optimized. Therefore AddressLib, a structured scheme for pixel addressing was developed, that can be accelerated by AddressEngine, a coprocessor for visual information processing. In this paper, the architectural design of AddressEngine is described, which in the first step supports a subset of the AddressLib. Dataflow and memory organization are optimized during architectural design. AddressEngine was implemented in a FPGA and was tested with MPEG7 Global Motion Estimation algorithm. Results on processing speed and circuit complexity are given and compared to a pure software implementation. The next step will be the sup...

• Type: Conference
• Year: 2005
• Where: DATE
• Authors: Walter Stechele, L. Alvado Cárcel, Stephan Herrmann, J. Lidón Simón
• Keywords: Architectural Design, DATE 2005, Hardware, Pixel Address Calculations, Visual Information Processing