High-diagnosability online built-in self-test of FPGAs via iterative bootstrapping

We develop a novel on-line built-in self-test (BIST) technique for testing FPGAs that has a very high diagnosability even in presence of clustered faults, a fault pattern for which previous BIST methods proved ineffective. Using an iterative bootstrapping process, our method first finds a faultfree test circuit in each BISTer tile and then tests the PLBs functionally using a fault-detection-and-gross-diagnosis phase followed by a time-efficient adaptive diagnosis phase. We establish the correctness of the deterministic phases of our BIST technique. We also analyze the probability of correct diagnosis by our BISTer in the presence of multiple random faults. Simulation results show that our BIST technique has very high fault coverage (98.7% for 25% fault density for random faults and 98.9% for 8.8% fault density for clustered faults) and low fault latency, and supports the theoretical analysis. Categories and Subject Descriptors B.7.0 [Integrated Circuits]: General; B.8.1 [Performanc...

• Type: Conference
• Year: 2005
• Where: GLVLSI
• Authors: Vishal Suthar, Shantanu Dutt
• Keywords: BIST Technique, Built-in Self-test, GLVLSI 2005, Random Faults, VLSI